Job Code:
101-0030

Location:
Bangalore, India

• Design of low-power standard cells, modifying cells to reduce power
• Work with backend team to complete place and route activities at full chip and route activities at full chip and module level
• Characterizing cells, generating lib files, running spice simulations, running DRC and LVS checks as well as GDSII generation

Qualifications:

• BSEE requiresd/MSEE preferred plus 3+ yrs experience
• Experience in design of std. cell
• Knowledge of low-power design techniques using 130nm or 65nm CMOS process
• Experience in tools used for design of std. cells like spice, schematic editor, LVS, DRC, and place and route tools.
• Good understanding of library creation process

Apply now at jobs@teranetics.com     Please include job code # in email subject line.

Job Code:
101-0031

Location:
Bangalore, India

• Verification of signal procession blocks used in 10G phy
• Integrating C/C++ models for various complex signal processing alorithms into the verification evironment

Qualifications:

• BSEE Required / MSEE Preferred plus 3+ yrs experience
• DSP experience required
• Knowledge of Verilog/Vera/SystemC or other industry standard verification tools

Apply now at jobs@teranetics.com     Please include job code # in email subject line.

Job Code:
101-0032

Location:
Bangalore, India

• Analog Mixed-Signal design, layout and testing of circuits/products
• Design challenges will include products/circuits for the areas of Power management, Gb Ethernet, RF, etc.
• Candidate could be expected to lead a block on a complex analog chip

Qualifications:

• BSEE/BTECH required / MSEE/MTECH preferred plus 3+ yrs experience
• Knowledge of basic analog building blocks such as op-amps, comparators, etc.
• Experience with at least one of the following areas (1) SERDES (2) Power Management ICs (3) RF (4) ADC-DAC (5) PLL/DLL
• Items (1) and (2) highly preferred
• Excellent fundamentals across fields of Device physics, Controls, Signals-Systems, E&M
• Familiarity with CADENCE simulation, layout and extraction tools (or other industry equivalents)

Apply now at jobs@teranetics.com     Please include job code # in email subject line.

Job Code:
101-0036

Location:
Bangalore, India

• Analog Mixed-Signal layout and verification for next gen high-speed analog circuits
• Will work on chip level floor-plan with limited supervision

Qualifications:

• BSEE/BTECH required / MSEE/MTECH preferred or extensive background in layout of high-performance analog circuits.
• Must have direct design or layout experience in at least one of the following areas: Nyquist Rate ADC's, Sigma-Delta ADC, DAC, Line drivers, Analog Filters, Programmable Gain Amplifiers, High-performance Analog Phase locked loops, high-speed SERDES.
• Familiarity with Cadence and Mentor CAD tools is required, preferablly familiar with Cadence Virtuoso, Composer, and verifications tools including Assura, Mentor Calibre LVS, DRC, XRC engines for verification
• Knowledge of working of basic analog building blocks such as op-amps, comparators, etc is a plus

Apply now at jobs@teranetics.com     Please include job code # in email subject line.

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