Senior ASIC / Methodology Engineer

Job description

As a senior member of our ASIC team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as: netlist manipulation, clocks, timing convergence, design for test, and low power operation. Specifically you' be focusing on methodologies for full chip layout planning (partitioning, planning clock distribution, power control and other structures), full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic.

Responsibilities: 

• Develop advanced methodologies for synthesis, chip level integration, floorplanning, physical partitioning, and low power design flow (CPF/UPF)
• Develop configurable timing flows using commercial timing tools for timing analysis and closure
• Develop scripts for performing ECO's.
• Collaborate and deploy methodologies for advanced design architectures.

Qualifications / Requirements:

• Bachelor's, Electrical Engineering or BS/MS Electrical Engineering
• Minimum 10 years experience with low power design methodology.
• Experience with Synthesis and STA tools.
• Experience with DFT tools
• Strong scripting skills